1. Field of the Invention
The present invention relates to power converter, and more specifically, the present invention relates to the control circuit and control method for power converter providing output regulation without input capacitor.
2. Description of Related Art
Nowadays, various power converters have been widely used to provide a regulated output (output voltage and/or output current). The power converter has an input capacitor for the energy store. Normally, the input capacitor is an electrolytic capacitor that is bulky and low reliability. Furthermore, without using a high value of input capacitor, the power factor (PF) of the power converter can be improved. Therefore, one of the objects of present invention is to eliminate the need of the input capacitor for improving the reliability of the power converter. Other objects of the present invention include improving the PF, reducing the size and the cost of the power converter.
FIG. 1 shows a prior art of a flyback power converter that has an input electrolytic capacitor 40 for the energy store. As shown in FIG. 1, the conventional flyback power converter includes a rectifier 12. The rectifier 12 receives an input line voltage VAC and rectifies the input line voltage VAC. The input electrolytic capacitor 40 is coupled to an output terminal of the rectifier 12 for the energy store. A voltage VDC is provided by the input electrolytic capacitor 40. A transformer 10 has a primary winding NP, a secondary winding NS and an auxiliary winding NA.
A terminal of the primary winding NP is coupled to receive the voltage VDC. Another terminal of the primary winding NP is coupled to a transistor 20. The transistor 20 is utilized to switch the transformer 10. A terminal of the secondary winding NS is coupled to a terminal of a rectifier 60. An output capacitor 65 is connected in between another terminal of the rectifier 60 and another terminal of the secondary winding NS for providing an output voltage VO to a load 70. The load 70 and the output capacitor 65 are connected in parallel.
A terminal of the auxiliary winding NA is coupled to a voltage divider. The voltage divider has resistors 51 and 52. The resistors 51 and 52 are connected in series. The voltage divider generates a voltage-sense signal VS. The resistor 52 is further coupled to the ground. A switching controller 50 is coupled to a joint point of the resistors 51 and 52 for receiving the voltage-sense signal V. The switching controller 50 generates a switching signal SW. The switching signal SW controls the transistor 20 to switch the transformer 10 for regulating an output (output current IO and/or the output voltage VO) of the power converter. When the transistor 20 is turned on, a switching current IP will flow through the transformer 10. Through a resistor 30, the switching current IP further generates a current-sense signal VCS. The current-sense signal VCS is coupled to the switching controller 50.
The waveforms of the input line voltage VAC and the voltage VDC are shown in FIG. 2. The voltage VDC is the voltage on the input electrolytic capacitor 40. The minimum voltage of the voltage VDC maintains the power converter operated properly. A low voltage of the voltage VDC may cause the feedback open loop of the power converter. The output voltage VO of the flyback power converter can be expressed as,
                              V          O                =                  N          ×                      V                          D              ⁢                                                          ⁢              C                                ×                                    T              ON                                      T              -                              T                ON                                                                        (        1        )            where the N is turn ratio of the transformer 10 (N=NS/NP; NP is the primary winding, NS is the secondary winding); the VDC is the voltage provided to the transformer 10; TON is the on-time of the transistor 20; T is the switching period of the transistor 20.
In order to achieve a stable feedback loop for the power converter and prevent the transformer saturation, the maximum duty cycle “TON/T” is limited, such as <80% in general. If the voltage VDC is too low, the maximum on-time TON will be unable to maintain the regulated output voltage VO (shown in equation (1)), which will cause the feedback open loop. When the feedback loop is significantly on/off in response to the change of the input line voltage VAC, an overshoot and/or undershoot signal can be easily generated at the output of the power converter.